9 meilleures offres (backend engineer (python)) (à pourvoir)

Lead Custom Design Engineer
Synthara AG —Zürich, ZH
- Niveau Doctorat
- Niveau Master
- Mentorat
Senior Test Automation Engineer (m/f/x)
Ekkiden —Genève, GE
- 100%
- C++
- Scripting
- Python
Postuler rapidement
il y a 4 jours
Senior System Engineer – 100%
WENET AG - Wealth Investment Network AG —Pfäffikon, SZ
- 100%
- JavaScript
- Développement logiciel
- Python
- Travail à domicile
Senior Layout Engineer
Synthara AG —Zürich, ZH
- Python
Senior Custom Design Engineer
Synthara AG —Zürich, ZH
- Niveau Doctorat
- Niveau Master
- Python
Tech Lead – Advanced Analytics
TotalEnergies —Genève, GE
- Gestion du personnel
- Niveau Doctorat
- Niveau Master
Senior R&D Engineer
Proton —Genève, GE
- Anglais
- Windows
- C++
Postuler rapidement
Technical Lead – Physical Design (RTL to GDSII)
Synthara AG —Zürich, ZH
- Python
Staff / Principal Machine Learning Engineer, Serving - Switzerland
Inworld AI —Suisse
- 100%
- Télétravail
- Niveau Doctorat
- Anglais
- Niveau Master
il y a 8 jours

Related jobs to explore

Based on your search for backend engineer (python)

Robotics Engineer Intern - Spatial AI & Intelligent Robotics
Flyability —Paudex, VD
Knowledge Integration: Investigate approaches for combining perception outputs with contextual and domain-specific information to support intelligent system…
Postuler rapidement
Junior Systems Test Engineer (H/F/X)
Ekkiden —Lausanne, VD
You will work on the definition and execution of test activities in the cleanroom, potential on-field assessments with dedicated instrumentation, and system…
Postuler rapidement
il y a 7 jours

Je souhaite recevoir la dernière alerte Emploi pour les postes de ce type : backend engineer (python)

En vous connectant à votre compte, vous acceptez les Conditions d'utilisation de SimplyHired et consentez à notre Politique relative aux cookies et Politique de confidentialité.

Afficher des offres d'emploi dans d'autres lieux

backend engineer (python) jobs near

Senior System Engineer, Pfäffikon, SZ : emplois

Technical Lead, Genf, GE : emplois

Senior Engineer, Zürich, ZH : emplois

Lead Designer, Zürich, ZH : emplois

Senior Design Engineer, Zürich, ZH : emplois

Senior System Engineer, Zürich, ZH : emplois

Senior System Engineer, Luzern, LU : emplois

Junior Software Engineer, Winterthur, ZH : emplois

Senior System Engineer, Genève, GE : emplois

Devops Engineer, Zürich, ZH : emplois

Technical Lead, Zürich, ZH : emplois

Java Lead, Genf, GE : emplois

Technical Sales Engineer, Zürich, ZH : emplois

Technical Lead, Genève, GE : emplois

Team Lead Business Intelligence, Kanton Zürich : emplois

Technical Lead, Lausanne, VD : emplois

Senior Engineer, Bern, BE : emplois

Field Service Engineer, Zürich, ZH : emplois

Software Engineer, St. Gallen, SG : emplois

Software Engineer, Luzern, LU : emplois

Lead Custom Design Engineer

Synthara AG
Zürich, ZH

Soumettre votre candidature

Détails de l'emploi

Qualifications

Niveau Doctorat
Niveau Master
Mentorat
Leadership
Python

Description complète du poste

Role

Location: Zürich, Switzerland
Seniority: 7+ years (custom digital, analog, or memory), team leadership

Lead the development of high-performance, custom based digital compute or SRAM memory designs to power our compute-in-memory SRAM (ComputeRAM®). You will own architecture, circuit design, verification, and silicon correlation for advanced nodes down to 5 nm and below, and you will lead a small team of custom designers and layout engineers to predictable, production-grade outcomes. Expect hands-on work on bitcell-adjacent periphery, datapath interfaces, optimizing data movement, as well as tight collaboration with full-custom layout, digital, backend, DFT, and test.

What you’ll do

Own the product roadmap: define specs, PPA targets, verification depth, and quality bars for new SRAM variants and CxR-adjacent custom blocks.
Design & verify memory or datapath subsystems, including sense amps, data drivers, multipliers, adders, register files, timing/control FSMs, etc..
Engineer for advanced nodes: close on variation (corners, Monte-Carlo), stability, noise/IR drop, device reliability, and wake-up/low-power behaviors in FinFET and FDSOI.
Integrate for product: define clean digital boundaries (standard-cell and bus interfaces), latency/handshake contracts, and timing budgets so blocks drop into a digital-on-top mixed-signal flow.
Silicon correlation: plan bring-up, build characterization benches, analyze ATE data, and publish correlation and errata with clear fixes.
Redundancy & test: specify and validate redundancy/repair schemes; work with DFT (MBIST and Scan) test coverage; sign off on a production test plan.
Partner with layout: co-plan floorplans, matching/guarding, shielding, and routing topologies; review extraction and fix EM/IR issues early.
Elevate method & team: coach designers, run reviews, enforce checklists, and grow automation (Python/Tcl) for regressions, reporting, and collateral generation.

Outcomes (first 18 months)

Tape-in and silicon of at least one production-grade CxR custom memory block meeting spec across PVT, with signed correlation and test reports.
A reusable design kit (models, constraints, verification plans, char scripts, checklists) that shortens the following variant’s cycle time.
A high-functioning custom team with clear ownership (periphery, timing/control, modeling, characterization) and reliable delivery metrics.
Quantified PPA and yield gains from design or methodology improvements you led.

Requirements

MS or PhD in Electrical/Computer Engineering (or similar) and 7+ years in custom digital, memory, or analog design.
Track record of end-to-end ownership of production-grade functional blocks, including sign-off and silicon correlation.
Deep understanding of high-performance and low-power circuit design on FinFET nodes (stability, variation, leakage, performance).
Experience leading a small team (mentoring, reviews, planning) and coordinating tightly with layout, digital, backend, DFT, and test.
Clear communication, structured documentation, and a quality-first mindset.

Nice to have

Scripting for design and characterization automation (Python, Tcl) and model/report generation.
Experience with memory compilers, characterization flows, and verification environments.
DTCO/STCO exposure to align device, bitcell, and periphery choices with product goals.
Background with production test strategies.
Familiarity with compute-in-memory constraints and with integrating custom memory into large digital systems.

Apply

Send your CV and a short note (2–3 paragraphs on a design you owned, your toughest bug & how you solved it, an intro on what you like to do and how you see yourself as an engineer)

Interview flow (indicative)

30-min intro with HR (role/context)

First Technical deep dive

Second Technical Deep Dive

(Optional) Third Technical Deep Dive

Systems/product conversation with management

Soumettre votre candidature

Affinez votre recherche

backend engineer (python) emplois

Lead Custom Design Engineer

Senior Test Automation Engineer (m/f/x)

Senior System Engineer – 100%

Senior Layout Engineer

Senior Custom Design Engineer

Tech Lead – Advanced Analytics

Senior R&D Engineer

Technical Lead – Physical Design (RTL to GDSII)

Staff / Principal Machine Learning Engineer, Serving - Switzerland

Related jobs to explore

Je souhaite recevoir la dernière alerte Emploi pour les postes de ce type : backend engineer (python)

Related Searches

Afficher des offres d'emploi dans d'autres lieux

Role

What you’ll do

Outcomes (first 18 months)

Requirements

Nice to have

Apply

Interview flow (indicative)

Outils pour les chercheurs d'emploi

Outils Employeurs

Parcourir

Garder le contact