5 meilleures offres (python, vaud) (à pourvoir)

Internship - Analog Design
Kandou AI —Saint-Sulpice, VD
- 100%
- Niveau Master
- Esprit d'analyse
- Compétences en communication
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il y a 1 jour
Endpoint Engineer
Swissquote Bank —Gland, VD
- 100%
- Microsoft Access
- Gestion du personnel
- Windows
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22 h
Digital Design Engineer
Kandou AI —Saint-Sulpice, VD
- 100%
- Travail hybride
- Gestion du personnel
- Niveau Doctorat
- Niveau Master
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il y a 1 jour
Internship - Communication System Modelling
Kandou AI —Saint-Sulpice, VD
- 100%
- Niveau Master
- Esprit d'analyse
- C++
Postuler rapidement
il y a 1 jour
Analog SerDes Architect
Kandou AI —Saint-Sulpice, VD
- 100%
- Travail hybride
- C++
- Niveau Licence
- Compétences en communication
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il y a 1 jour

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Internship - Analog Design

Kandou AI
Saint-Sulpice, VD

Postuler rapidement

Détails de l'emploi

100%
Il y a 1 jour

Qualifications

Niveau Master
Esprit d'analyse
Compétences en communication
Python

Description complète du poste

Kandou is redefining AI infrastructure through innovative interconnect technologies that significantly reduce power consumption while maintaining high bandwidth and ultra-low latency. Our mission is to make AI systems more scalable, efficient, and accessible.

Today we have one internship position available for max 6 months, in our Advanced R&D, for MSc students in the following area :

Analog Design Intern

Internship Background

Modern computing systems increasingly rely on high-speed serial interfaces to transfer large volumes of data between processors, memory devices, and accelerator chips. Simultaneous bidirectional (SBD) signalling enables both ends of a copper channel to transmit and receive data concurrently over the same physical medium, offering a promising path toward higher bandwidth efficiency without increasing the number of interconnects.

Project Objectives

The objective of this internship is to investigate circuit and signal-processing techniques that enable simultaneous bidirectional communication over wideband copper serial links. The student will explore methods for separating the locally transmitted signal from the incoming signal while maintaining high data rates and robust link performance.

Specific goals may include:

Reviewing the state of the art in simultaneous bidirectional and full-duplex wireline communication systems;
Developing behavioural models of wideband copper channels and transceiver architectures;
Studying self-interference cancellation techniques in the analog and/or digital domains;
Evaluating the impact of channel impairments, mismatch, and non-idealities on link performance;
Designing and simulating key building blocks using Python or circuit-level CAD tools;
Assessing achievable data rates, energy efficiency, and implementation complexity.

Expected Outcomes

At the end of the internship, the student is expected to:

Gain hands-on experience in the design and analysis of high-speed wireline communication systems;
Develop simulation models for simultaneous bidirectional serial links;
Quantify the benefits and challenges associated with full-duplex operation over copper channels;
Present the obtained results in a technical report and oral presentation.

Depending on the progress and interests of the student, the work may lead to conference or journal publication opportunities.

Desired Background

The project is suitable for motivated Master's students in Electrical Engineering, Microelectronics, Communications Engineering, or Computer Engineering.

Preferred qualifications:

Good level of familiarity with analog IC design and layout drawing;
Familiar with analog circuit simulators (SPICE/SPECTRE);
Strong background in signal processing;
Strong communication and presentation skills.

If you recognize yourself in the description above, and love to be part of a growing Company, are a good team player with an upbeat approach to life, we would love to hear from you. Together We Kandou It!

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python emplois - vaud

Internship - Analog Design

Endpoint Engineer

Digital Design Engineer

Internship - Communication System Modelling

Analog SerDes Architect

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