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Senior Digital Design and Verification Engineer

Synthara AG
Zürich, ZH

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Détails de l'emploi

Qualifications

Compétences rédactionnelles
ARM
Python

Description complète du poste

Role

Location: Zürich, Switzerland
Seniority: 6 years

Own the design and verification of part of our digital IP portfolio that wraps and integrates our compute-in-memory technology(ComputeRAM®): clean, synthesis-ready SystemVerilog RTL, plus UVM environments that reach coverage closure and de-risk silicon. You’ll specify and build register/bus interfaces, DMA, and control logic. Expect tight collaboration with custom design, backend, and software teams to hit PPA, coverage, and time-to-tapeout simultaneously.

What you’ll do

Implement RTL: memory-mapped control blocks, AXI/AHB/APB bridges, FIFOs/scoreboards, arbiters, DMA, and datapaths; write synthesis-friendly code with a clear reset/CDC strategy.
Extreme optimization for power, with a power-driven mindset and approach to design
Develop UVM testbenches (agents, sequencers, predictors, scoreboards); drive constrained-random + directed testing; close coverage (func/code/assertion).
GLS: run gate-level sims with SDF for critical paths; support FPGA prototypes for early HW/SW bring-up.
Documentation & specs: write IP/user guides, register maps, programming models; contribute reusable UVM components and regression infrastructure for the team.

Outcomes (first 18 months)

Tape-in of one or more IPs (or a subsystem) with coverage goals met (functional/code/assertion) and lint/CDC/RDC clean sign-off packages.
Demonstrated GLS/SDF pass on the IP’s top-risk paths and correlation to FPGA results; Achieve sign-off quality.
A reusable UVM kit (agents/sequences/scoreboards) and CI scripts that cut regression time and raise pass-rate stability across projects.

Requirements

5+ years in digital design or verification for ASIC; strong SystemVerilog RTL and basic understanding of UVM
Hands-on experience with either RISC-V or ARM architectures, either as a system-level integrator or as a designer.
Knowledge of synthesis basics and how RTL choices impact timing/power/area
Clear technical communication, ability to work with structured specs, and habit of turning one-off designs into reusable components.

Nice to have

Experience verifying memory-adjacent IP (SRAM controllers/periphery, MBIST/scan integration) and power-aware/UPF simulation flows.
AMBA (AXI/AHB/APB) protocols, clock/reset schemes, CDC handshakes, FIFOs, arbiters; comfortable writing SVAs.
GLS proficiency (SDF back-annotation), familiarity with FPGA bring-up and HW/SW test harnesses.
Python/Tcl for stimulus generation, log parsing, coverage triage
Background in AI/DSP accelerators or quantized dataflows (helpful context for CxR use-cases).

Apply

Send your CV and a short note (2–3 paragraphs on a design you owned, your toughest bug & how you solved it, an intro on what you like to do and how you see yourself as an engineer)

Interview flow (indicative)

30-min intro with HR (role/context)

First Technical deep dive

Second Technical Deep Dive

(Optional) Third Technical Deep Dive

Systems/product conversation with management

Soumettre votre candidature

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backend engineer (python) emplois

Senior Digital Design and Verification Engineer

Senior Custom Design Engineer

Member of Technical Staff – AI Inference platform, features

Senior Layout Engineer

Technical Lead – Physical Design (RTL to GDSII)

Staff / Principal Machine Learning Engineer, Serving - Switzerland

Other jobs to consider

Je souhaite recevoir la dernière alerte Emploi pour les postes de ce type : backend engineer (python)

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