12 meilleures offres (computing systems engineer) (à pourvoir)

Standard Custom Design Engineer
Synthara AG —Zürich, ZH
- Niveau Doctorat
- Niveau Master
- Python
Tech Lead
Verity —Zürich, ZH
- 100%
- Gestion du personnel
- Anglais
- AWS
Senior Compiler Engineer
NVIDIA —Zürich, ZH
- 100%
- Niveau Master
- C++
- Niveau Licence
Research Engineer, Production Model Post-Training
Anthropic —Zürich, ZH
- Travail le week-end
- Niveau Licence
- Compétences en communication
- Python
- Congé parental payé
DevOps Engineer III (Data Platform)
Bundesverwaltung - Eidgenössisches Departement für Verteidigung, Bevölkerungsschutz und Sport VBS —Wald, ZH
- Anglais
- Linux
il y a 12 jours
Senior GPU Networking Architect
NVIDIA —Zürich, ZH
- De 292 500 CHF à 650 000 CHF par an
- 100%
- Informatique
- Compétences rédactionnelles
- Niveau Master
Senior Compiler Engineer
NextSilicon —Zürich, ZH
- Niveau Doctorat
- Niveau Master
- C++
Postuler rapidement
PostDocs and/or Senior Engineers in Electromagnetics
IT'IS Foundation —Zürich, ZH
- Niveau Doctorat
- Anglais
- C++
(Senior) VMware Solution Architect – 100%
SOULTEC AG —Dübendorf, ZH
- 100%
- Anglais
- Aide au transport
HPE Labs - EMEA Research Lab Ph.D. Intern
Hewlett Packard Enterprise —Bâle, BS
- 100%
- Niveau Doctorat
- Recherche
- Niveau Master
Machine Learning Engineer
Giotto.ai —Lausanne, VD
- 100%
- Télétravail
- Niveau Doctorat
- Python
Postuler rapidement
Sales Engineer (DACH Region)
Fortanix —Suisse
- 100%
- Télétravail
- AWS
- Scripting
- Python
Postuler rapidement

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Standard Custom Design Engineer

Synthara AG
Zürich, ZH

Soumettre votre candidature

Détails de l'emploi

Qualifications

Niveau Doctorat
Niveau Master
Python

Description complète du poste

Role

Location: Zürich, Switzerland
Seniority: MS +4 years or PhD

Own critical mixed-signal subsystems that bring our compute-in-memory SRAM (ComputeRAM®) from design to silicon and into production. You will design, verify, and characterize custom blocks, including full-custom digital datapaths and memories, and collaborate tightly with our digital and layout teams to hit aggressive PPA and quality targets on modern CMOS nodes, down to 4nm and below. You will deal with multi-disciplinary topics ranging from traditional mixed-signal design to solving digital timing constraints.

What you’ll do

Design & verify mixed-signal circuits/subsystems for ASICs (architecture, transistor-level design, simulation, corners/Monte-Carlo, modelling).
Develop AI-related building blocks as part of our in-memory computing technology.
Partner across disciplines on interfaces, buses/standard-cell boundaries, and timing/power budgets.
Contribute to IP-quality specifications, reviews, reusable verification collateral, and documentation ready for internal reuse and customer delivery.
Continuously improve flows through scripting/automation (e.g., Python/Tcl) for characterization, report generation, and regressions, guaranteeing reproducibility and reliability. (Nice-to-have but valued.)

Outcomes (first 18 months)

Complete and document one or more IP blocks
Tape-in and silicon of at least one sub-system meeting spec across PVT; complete post-production test plan and correlation report signed off.

Requirements

Hands-on sub-28 nm CMOS experience
Quality-oriented approach
Proven design ownership in one or more of: datapath/standard cells design, memory/SRAM design, data-converters, ultra-low-power amps, power-management, references, PLLs, sensor signal processing chains.
Clear technical communication; structured planning; comfort working cross-functionally with digital/custom/layout.

Nice to have

Exposure to datapath/arith/bus/standard-cell co-design boundaries (device-level parasitics, signal-integrity hand-offs, and glitch reduction).
Scripting for automation (Python/Tcl) in mixed-signal flows
Familiarity with compute-in-memory or memory-periphery constraints (matching, IR/EM, variation, testability)

Apply

Send your CV and a short note (2–3 paragraphs on a design you owned, your toughest bug & how you solved it, an intro on what you like to do and how you see yourself as an engineer)

Interview flow (indicative)

30-min intro with HR (role/context)

First Technical deep dive

Second Technical Deep Dive

(Optional) Third Technical Deep Dive

Systems/product conversation with management

Soumettre votre candidature

Affinez votre recherche

computing systems engineer emplois

Standard Custom Design Engineer

Tech Lead

Senior Compiler Engineer

Research Engineer, Production Model Post-Training

DevOps Engineer III (Data Platform)

Senior GPU Networking Architect

Senior Compiler Engineer

PostDocs and/or Senior Engineers in Electromagnetics

(Senior) VMware Solution Architect – 100%

HPE Labs - EMEA Research Lab Ph.D. Intern

Machine Learning Engineer

Sales Engineer (DACH Region)

More jobs to discover

Je souhaite recevoir la dernière alerte Emploi pour les postes de ce type : computing systems engineer

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