2 meilleures offres (computing systems engineer) (à pourvoir)

Principal Cadence Layout Engineer
M/A Com Technolgy Solutions —Zürich, ZH
- Niveau Licence
il y a 2 jours
Senior Marketing Manager
Domera Labs —Zürich, ZH
- De 65 000 CHF à 100 000 CHF par an
- 100%
- Leadership
- Python
Postuler rapidement
10 h

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Principal Cadence Layout Engineer

M/A Com Technolgy Solutions -
Zürich, ZH

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Détails de l'emploi

Il y a 2 jours

Qualifications

Niveau Licence

Description complète du poste

MACOM (NASDAQ: MTSI) is a global leader in the design and manufacture of advanced semiconductor products across a diverse range of end markets, including Data Centers, Telecommunications, Industrial and Aerospace and Defense. We develop innovative, cutting-edge technologies and products across the spectrum of radio frequency (RF), microwave, millimeter wave, photonics and high-speed analog technologies. Our solutions support critical network infrastructure applications like artificial intelligence, high performance computing, satellite communications, radar, unmanned aerial vehicles, medical equipment, test and measurement and advanced wireless networks.

MACOM has more than 75 years of expertise in semiconductor process development, wafer fabrication, circuit design, advanced packaging, systems architecture and applications engineering. We are committed to our customers’ success. We partner with customers to help solve their most challenging problems by providing semiconductor solutions that are at the forefront of the highest power, highest frequency and/or highest data rates.

Leading technologies, innovative products and driven employees. Come be a part of MACOM and help advance the next generation of connectivity infrastructure!

Role Description

In this role the layout engineer will closely work with the design team to layout and verify custom analog/mixed-signal IPs
Lead full-custom IC layout design and verification, including chip floor planning, analog IP layout and chip level layout integration of various analog, mixed-signal and ASIC blocks
Full verification of Block level and top-level layout including extraction, DRC, LVS, and DFM checking
Layout schedule planning and working with other IP layout engineers to integrate various layout blocks
Co-work with designers on block level and top-level floor planning
Layout review for power/gnd routing, electro migration, signal path check, matching, and signal coupling

Qualifications

High-speed layout design expertise with good understanding of parasitics
Minimum 10 years of custom layout experience
Knowledge of Cadence Virtuoso design flow
High level proficiency in interpretation of CALIBRE DRC, ERC, LVS reports.
Full understanding of IR drop, RC delay, Electromigration and chip finishing
Ability to do floor planning and do area estimate
Good communication with circuit designers and other layout engineers
Familiarity with high-speed BiCMOS layout is a plus
Scripting in Cadence is a plus
At a minimum, Bachelor degree in Engineering

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