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Programmable Logic Design Engineer

Viasat, Inc. -
Lausanne, VD

Soumettre votre candidature

Détails de l'emploi

100% | Temps de travail : 90-100%

Avantages

Logement

Qualifications

MATLAB
Niveau Licence
GitHub
Compétences en communication

Description complète du poste

About us:

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.

What you'll do:

In this role you will help develop FPGA designs for Viasat next generation terminal products, including interfaces and high speed signal processing algorithms and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements' phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration.

The day-to-day:

Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications
Develop testbenches and help maintain and update system level verification environment
Synthesize Verilog and System Verilog for Altera and Xilinx/AMD FPGAs
Develop timing constraints, analyze timing results, and implement design changes required to close timing
Generate and collaborate on required design documents, development requirements, specifications and verification protocols
Responsible for owning and driving technical issues to resolution
Integrate and debugs design in the laboratory

What you'll need:

Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
10-12 years FPGA design experience, including Altera Quartus and Xilinx Vivado
Strong knowledge of System Verilog
Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders
Proven track record to design and implement FPGA modules using System Verilog with simulation and testbench development
Work independently, take initiative, and take ownership of tasks and results
Strong written and verbal communication skills, ability to work with a geographically distributed team

What will help you on the job:

Familiarity with Matlab
Experience with GitHub
Experience with developing code for legacy Viasat modem platforms
Understanding and knowledge of Satellite communication waveforms and standards

: At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat’s comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits. EEO statement:

Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.

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Affinez votre recherche

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Je souhaite recevoir la dernière alerte Emploi pour les postes de ce type : it systems engineer (vaud)

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