6 meilleures offres (computing systems engineer) (à pourvoir)

Low Latency MM Engineer
G-20 Group —Zürich, ZH
- 100%
- Assemblage
- C++
- Réseaux informatiques
Postuler rapidement
il y a 10 jours
Senior Staff Forward Deployed Engineer, GenAI, Google Cloud
Google —Zürich, ZH
- 100%
- Niveau Doctorat
- Niveau Master
- Niveau Licence
il y a 10 jours
Senior Site Reliability Engineer, DGX Cloud
NVIDIA —Zürich, ZH
- 100%
- Niveau Master
- AWS
- Réseaux informatiques
il y a 5 jours
Software Engineer III, Search Quality
Google —Zürich, ZH
- 100%
- Informatique
- Niveau Doctorat
- Niveau Master
il y a 10 jours
OT Technical Lead (m/w/d) - Your next role?
Givaudan —Vernier, GE
- Travail hybride
- Informatique
- Anglais
- Windows
- Congés payés
- Congé pour raisons familiales
Principal Cadence Layout Engineer
M/A Com Technolgy Solutions —Zürich, ZH
- Niveau Licence
il y a 5 jours

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Low Latency MM Engineer

G-20 Group
Zürich, ZH

Postuler rapidement

Détails de l'emploi

100% | Temps de travail : 90-100%
Il y a 10 jours

Qualifications

TCP
Assemblage
C++
Équipement informatique
Gestion des risques
Réseaux informatiques
Linux
Compétences en communication

Description complète du poste

About G20 Group

G-20 Group is a cross-asset trading firm headquartered in Switzerland, trading delta-one and derivatives markets globally. We combine startup agility with institutional-grade experience in proprietary trading, technology, and quantitative finance.

Role Overview

We are hiring for a Low Latency Market Making Engineer to design, build, and continuously optimize the systems responsible for quote generation and order execution within microsecond-level latency tolerances. This role sits combines deep knowledge of software engineering, hardware, and market microstructure, and requires close collaboration with traders and quantitative researchers to translate strategy requirements into production systems capable of achieving favorable queue position across trading venues.

Responsibilities

Design, build, and maintain ultra-low-latency market making systems, including order entry, market data processing, risk controls, and quote and order management functionality
Continuously profile and optimize the tick-to-trade path, from network interface through kernel to application, with close attention to CPU cache behavior, memory layout, branch prediction, and lock-free data structures
Collaborate with hardware engineers, or develop FPGA logic directly depending on background, to minimize latency in critical-path processing
Own exchange connectivity, including implementation and maintenance of FIX, ITCH/OUCH, or proprietary binary protocols for order entry and market data feeds
Partner with traders and quantitative researchers to implement and calibrate quoting logic, risk controls, and inventory management in production environments
Build and maintain simulation, backtesting, and replay infrastructure to validate strategy and system changes prior to live deployment
Monitor live trading systems, diagnose latency regressions and operational anomalies in real time, and lead root-cause resolution efforts
Contribute to capacity planning and infrastructure decisions relating to co-location, network topology, and hardware upgrades
Uphold rigorous engineering standards, including code review, testing, deployment safety, and change management practices appropriate for systems executing live capital.

Requirements

Currently pursuing or recently completed a degree in Computer Science, Engineering, Mathematics, Data Science, Economics, Business, or a related field, top-tier university preferred
Strong proficiency in C++ (modern C++17/20 preferred), with the ability to reason about assembly output and compiler behavior
Thorough understanding of computer architecture, including CPU caches, NUMA, memory ordering, and kernel bypass networking technologies (e.g., Solarflare/OpenOnload, DPDK, or comparable solutions)
Experience with low-latency networking and associated protocols (TCP/UDP internals, multicast, kernel bypass) as well as exchange connectivity protocols such as FIX, ITCH, or OUCH
Solid understanding of Linux internals, including scheduling, interrupt handling, NUMA pinning, and huge pages, with demonstrated experience tuning production systems at the operating system level
Working knowledge of market microstructure, including order books, matching engine behavior, queue position, adverse selection, and inventory risk management practices employed by market makers
Experience with FPGA development (Verilog/VHDL) is advantageous, though not a strict requirement for all candidates
Demonstrated experience working on systems where microsecond- or nanosecond-level performance was critical, such as high-frequency trading, market making, exchange technology, or comparable latency-sensitive domains (telecommunications, high-performance computing, real-time systems)
Strong debugging and profiling capabilities using tools such as perf, VTune, or custom tracing and timestamping infrastructure
Strong communication skills and the ability to collaborate effectively with trading personnel under time-sensitive conditions during market hours.

Preferred / Desirable Experience

Experience building or tuning matching engines or exchange-side systems
Exposure to FPGA-based trading systems or programmable networking hardware (e.g., Solarflare, Exablaze, Arista MetaWatch)
Prior experience at a market making firm, high-frequency trading firm, or exchange technology vendor.

Locations and Right to work: This role can be based out of our Zurich, London, New York or Hong Kong office. Only candidates who possess the pre-existing right to work in one of the locations above without company sponsorship need apply.

Join G-20 and be a part of a team that is at the forefront of financial markets, driving innovation and excellence in the sector.

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computing systems engineer emplois

Low Latency MM Engineer

Senior Staff Forward Deployed Engineer, GenAI, Google Cloud

Senior Site Reliability Engineer, DGX Cloud

Software Engineer III, Search Quality

OT Technical Lead (m/w/d) - Your next role?

Principal Cadence Layout Engineer

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